From 78a9eb8fbffb496ab22e2becee82822c41b72e98 Mon Sep 17 00:00:00 2001 From: "Eugeniy E. Mikhailov" Date: Thu, 7 Apr 2022 17:19:08 -0400 Subject: redone current settling based on realistic precision --- qolab/hardware/power_supply/keysight_e3612a.py | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'qolab/hardware/power_supply') diff --git a/qolab/hardware/power_supply/keysight_e3612a.py b/qolab/hardware/power_supply/keysight_e3612a.py index 168e7b3..a7159f4 100644 --- a/qolab/hardware/power_supply/keysight_e3612a.py +++ b/qolab/hardware/power_supply/keysight_e3612a.py @@ -107,7 +107,7 @@ class KeysightE3612A(PowerSupplySCPI): return( float(rstr) ) @BasicInstrument.tsdb_append - def setChanIout(self, chNum, val, currentPrecision=5e-6, currentHeadRoom=1e-3, dwellTime=0.3): + def setChanIout(self, chNum, val, currentHeadRoom=1e-3, dwellTime=0.3): """ Tuning Vout to achieve desired Iout. Generally setting current limit will maintain current near but not exact to desired. @@ -123,14 +123,20 @@ class KeysightE3612A(PowerSupplySCPI): # In general, once we estimate resistance of the load + source, we do not need to # anything extra. But there is a problem: for a given Vlimit setting, the actual Vout # is slightly off. + # We will assume that Vlimit = R*Iout + Vo = Vout + Vo, i.e. linear approximation for i in range(10): iOut=self.getChanIout(chNum) - if abs(iOut-iDesired) <= currentPrecision: + if abs(iOut-iDesired) <= self.getChandI(chNum): break vOut=self.getChanVout(chNum) + if self.getChanRegulation(chNum) == 2: # i.e. CV mode + vLimit=self.getChanVlimit(chNum) + Vo = vLimit - vOut + else: + Vo=0 R=vOut/iOut vDesired = R*iDesired - self.setChanVlimit(chNum, vDesired) + self.setChanVlimit(chNum, vDesired+Vo) time.sleep(dwellTime) @BasicInstrument.tsdb_append -- cgit v1.2.3