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authorEugeniy E. Mikhailov <evgmik@gmail.com>2022-05-31 13:39:05 -0400
committerEugeniy E. Mikhailov <evgmik@gmail.com>2022-05-31 13:39:05 -0400
commitdacb81b545524ccf5d5a012c8e284064fb3cced3 (patch)
treedad79ed7fa19a546c808d82984b3a49ed0f7afeb /qolab
parentfadcbdac7836579bed05f9598eb5a06654a24f9c (diff)
downloadqolab-dacb81b545524ccf5d5a012c8e284064fb3cced3.tar.gz
qolab-dacb81b545524ccf5d5a012c8e284064fb3cced3.zip
added default resistance, to check against edge case
If Vout set to 0, it is often report negative values, which messes up resistance estimate. So default resistance helps against such edge cases.
Diffstat (limited to 'qolab')
-rw-r--r--qolab/hardware/power_supply/keysight_e3612a.py6
1 files changed, 5 insertions, 1 deletions
diff --git a/qolab/hardware/power_supply/keysight_e3612a.py b/qolab/hardware/power_supply/keysight_e3612a.py
index 6793088..cb0b5de 100644
--- a/qolab/hardware/power_supply/keysight_e3612a.py
+++ b/qolab/hardware/power_supply/keysight_e3612a.py
@@ -11,6 +11,7 @@ class KeysightE3612A(PowerSupplySCPI):
self.numberOfChannels = 3
self.deviceProperties = {'OpMode', };
self.channelProperties = {'IsOn', 'Regulation', 'Vout', 'Vlimit', 'Iout', 'Ilimit', 'dV', 'dI', }
+ self.deffaultChannelR = 47; # used if no empirical way to calculate it via Vout/Iout
def getChandV(self, chNum):
"""
@@ -141,7 +142,10 @@ class KeysightE3612A(PowerSupplySCPI):
Vo = vLimit - vOut
else:
Vo=0
- R=vOut/iOut
+ if (iOut == 0) or (vOut <= 0.001): # when vOut set to 0 the numbers are misreported
+ R = self.deffaultChannelR # some default
+ else:
+ R=vOut/iOut
vDesired = R*iDesired
self.setChanVlimit(chNum, vDesired+Vo)
time.sleep(dwellTime)